The present invention relates to solid-state image pickup devices represented by CMOS image sensors, and to camera systems.
In recent years, CMOS image sensors have been attracting attention as solid-state image pickup devices (images sensors), in place of CCDs.
This is because CMOS image sensors overcome problems including that a dedicated manufacturing process is necessary for fabricating CCD pixels, a plurality of power supply voltages are necessary for the operation thereof, and a system becomes very complicated due to the necessity of a plurality of peripheral ICs to be operated in a combined manner.
CMOS image sensors can be manufactured using a manufacturing process similar to the process of manufacturing general CMOS ICs. Also, a CMOS image sensor can be driven by a single power supply. Furthermore, an analog circuit and a logic circuit using CMOS processes can be mixed in a single chip, resulting in a reduction of the number of peripheral ICs. That is, CMOS sensors have multiple advantages.
An output circuit of a CCD is generally a 1-channel (ch) output using an FD amplifier with a floating diffusion layer (FD: Floating Diffusion).
In contrast, a CMOS image sensor has an FD amplifier in each pixel and generally uses a column-parallel output scheme that selects a row from an array of pixels and simultaneously reads and outputs signals from the pixels in the selected row in a column direction.
Because it is difficult to obtain sufficient drive power using the FD amplifiers arranged in the pixels, the data rate is necessary to be dropped. In this sense, parallel processing is regarded to be advantageous.
In solid-state image pickup apparatuses represented by CCD and CMOS image sensors, miniaturization is further carried out because of a further increase in the number of pixels. In parallel to this, high-speed signal reading processing is required.
As means for realizing high-speed reading in a CMOS image sensor, pixels arranged two-dimensionally are configured to share signal reading lines in a vertical direction. Additionally, reading circuits are provided for individual columns, and, by driving them at the same time, simultaneous signal processing corresponding to the total number of columns is performed.
Also, generally in analog signal processing, high-speed processing and low-noise processing contradict each other. Thus, high-speed analog signal processing has problems that may lead to image quality degradation.
In contrast, the above-described reading circuits for the individual columns perform processing up to analog-to-digital conversion. Processing of items of column data corresponding to one to a few buses becomes digital signal processing, whereby significantly high-speed processing and a noise-robust circuit can be realized.
Various types of signal output circuits in column-parallel-output CMOS image sensors have been proposed. One of the most advanced types is the type that includes an analog-to-digital converter (hereinafter abbreviated as ADC (Analog digital converter)) in each column, and that obtains a pixel signal as a digital signal.
A CMOS image sensor with column-parallel ADCs is disclosed in, for example, W. Yang, et al. (W. Yang et al., “An Integrated 800×600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, February, 1999), and in Japanese Unexamined Patent Application Publication No. 2005-303648 and Japanese Unexamined Patent Application Publication No. 2005-323331.
FIG. 1 is a block diagram illustrating a structure example of a solid-state image pickup device (CMOS image sensor) with column-parallel ADCs.
This solid-state image pickup device 1 includes a pixel array section 2 serving as an image pickup unit, a row scanning circuit 3, a column scanning circuit 4, a timing control circuit 5, an ADC group 6, a digital-to-analog converter (hereinafter abbreviated as DAC (Digital-Analog converter) 7, and a data output circuit 8 including a sense amplifier circuit (S/A).
The pixel array section 2 is configured by arranging unit pixels 2-1, each including a photodiode and an intra-pixel amplifier, arranged in a matrix.
Also, in the solid-state image pickup device 1, the timing control circuit 5 for generating an internal clock, the row scanning circuit 3 for controlling row addresses and row scanning, and the column scanning circuit 4 for controlling column addresses and column scanning are arranged as control circuits for sequentially reading signals from the pixel array section 2.
The ADC group 6 includes ADCs 6A arranged for individual column lines V0, V1, . . . in a manner correlated with the individual columns of the pixel matrix. The ADCs 6A include (n+1) comparators 6-1 each of which compares a ramp waveform RAMP, which is obtained by changing a reference voltage generated by the DAC 7, which serves as a reference-voltage generating circuit, to be a stepped voltage, with an analog signal obtained for each row line H0, H1, . . . from unit pixels 2-1 through the column line V0, V1, . . . , asynchronous up/down counters (hereinafter called counters) 6-2 each of which performs counting up (or counting down) in response to an output of a corresponding one of the comparators 6-1 and a clock CK and includes a memory (latch) 6-5 that holds a count value, the memories (latches) 6-5 (illustrated in FIG. 2) that hold count values of the counters 6-2, and switches 6-4 selectively making connections between outputs of the counters 6-2 and the memories 6-5 in response to a signal SEL. Accordingly, a column-parallel ADC block 6-3 is configured.
Outputs of the individual counters 6-2 are connected via the switches 6-4 to a data transfer signal line 9.
The data output circuit (digital-signal processing circuit) 8 including the sense amplifier circuit corresponding to the data transfer signal line 9 and a subtracting circuit is arranged on the data transfer signal line 9.
At an initial time, each counter 6-2 having a function as a holding circuit enters a counting up (or counting down) state, and performs reset counting. When an output COMPOUTi of a corresponding one of the comparators 6-1 is inverted, the counter 6-2 terminates a counting up operation, and the count value is held in the memory 6-5.
On this occasion, the initial value of the counter 6-2 is an arbitrary value of an AD-converted gradation level, such as 0. In this reset counting period, the counter 6-2 reads a reset component ΔV of the unit pixel 2-1.
Thereafter, the counter 6-2 enters a counting down state, and performs data counting in accordance with the intensity of incident light. When the output COMPOUTi of the corresponding comparator 6-1 is inverted, the count value in accordance with a comparison period is held in the memory 6-5.
The count value held in the memory 6-5 is scanned by the column scanning circuit 4 and input as a digital signal to the data output circuit 8 via the data transfer signal line 9.
Here, the operation of the solid-state image pickup device (CMOS image sensor) 1 will be described.
After reading for the first time from the unit pixels 2-1 on an arbitrary row Hx to the column lines V0, V1, . . . becomes stable, the DAC 7 inputs a ramp waveform RAMP, which is obtained by temporally changing a reference voltage to be a stepped voltage, to each comparator 6-1. Comparison with a voltage of an arbitrary column line Vx is performed in a corresponding one of the comparators 6-1.
In parallel to inputting of the stepped wave having the ramp waveform RAMP, each counter 6-2 performs counting for the first time.
Here, an output of the comparator 6-1 is inverted when the RAMP voltage and the Vx voltage become equal. Accordingly, the count operation of the counter 6-2 is terminated, and a count value in accordance with the comparison time is held in the memory 6-5.
At the time of this reading for the first time, the counter 6-2 reads a reset component ΔV of the unit pixel 2-1. In the reset component ΔV, noise differing from one unit pixel 2-1 to another unit pixel 2-1 is included as offset.
However, variations in the reset components ΔV are generally small. Also, since the reset level is common to all pixels, an output of an arbitrary column line Vx is roughly known in advance.
Therefore, at the time of reading the reset component ΔV for the first time, the comparison period can be shortened by adjusting the ramp waveform (RAMP) voltage. In this case, for example, ΔV is compared in a count period (128 clocks) corresponding to 7 bits.
In reading for the second time, besides the reset component ΔV, a signal component in accordance with the intensity of incident light which is different for each unit pixel 2-1 is read, and an operation similar to that in reading for the first time is performed.
That is, after reading for the second time from the unit pixels 2-1 on an arbitrary row Hx to the column lines V0, V1, . . . becomes stable, the DAC 7 inputs a ramp waveform RAMP, which is obtained by temporally changing a reference voltage to be a stepped voltage, to each comparator 6-1. Comparison with a voltage of an arbitrary column line Vx is performed in a corresponding one of the comparators 6-1.
In parallel to inputting of the stepped wave having the ramp waveform RAMP, each counter 6-2 performs counting for the second time.
Here, an output of the comparator 6-1 is inverted when the RAMP voltage and the Vx voltage become equal. At the same time, a count value in accordance with the comparison time is held in the memory 6-5.
On this occasion, the count values obtained in counting for the first time and the second time are held at different places in the memory 6-5.
After the end of the foregoing AD conversion period, with the column scanning circuit 4, n-bit digital signals which are obtained for the first time and the second time and held in the memories 6-5 are transferred via the data transfer signal line 9 and detected at the data output circuit 8. After (signal for the second time)−(signal for the first time) is sequentially performed by the subtracting circuit, the difference is output to the outside. Thereafter, a similar operation is sequentially repeated for the individual rows, and a two-dimensional image is generated.
The foregoing operation is performed in one horizontal unit period (1H).
In 1H, reading for the first time from the unit pixels 2-1 on an arbitrary row Hx to the column lines V0, V1, . . . is denoted by P-phase reading PR; comparison for the first time in the comparators 6-1 is denoted by P-phase comparison PC; reading for the second time is denoted by D-phase reading DR; comparison for the second time in the comparators 6-1 is denoted by D-phase comparison DC; and post-processing after the D-phase processing is denoted by D-phase post-processing DAP. These individual operations are consecutively performed.
Control of timing of the P-phase reading PR, the P-phase comparison PC, the D-phase reading DR, the D-phase comparison DC, and the D-phase post-processing DAP is performed by the timing control circuit 5.
The above-described example is a circuit structure that performs integration-type analog-to-digital conversion processing using counters, comparators, and a reference voltage that is a RAMP wave.
At first, the counters 6-2 each store AD-converted digital data. This is transferred to another digital data storage region, and continuously, the next AD conversion is performed. At the same time, the data moved to the different place is sequentially accessed on a column-by-column basis, and the data is transferred in a horizontal direction and sent to the digital-signal processing circuit.
That is to say, the AD-conversion processing and the horizontal transfer processing are processed in a pipeline manner, whereby high-speed signal reading processing is realized.
The key problem here is the fact that a layout region that can be used for a column reading circuit is limited to the width of a miniature pixel.
Consequently, the reading circuit of each column becomes a vertically very long structure, and, due to the layout constraint, the number of signal lines that can be passed in the vertical direction becomes limited.
Because of the constraint, when the circuit is laid out, the circuit layout becomes such as that illustrated in FIG. 2.
FIG. 2 is a diagram illustrating a layout example of a column reading circuit.
In FIG. 2, reference numeral 6-5 denotes memories; CDT denotes intra-column data transfer control signals using the timing control circuit 5; and LHTC-1, LHTC-2, . . . denote column-direction (horizontal direction) control lines.
Also, data transfer signal lines 9-1, 9-2, 9-3, . . . are arranged at many stages.
The data storage regions (latch circuits) 6-5 for horizontal transfer are arranged between individual bits of the counters 6-2. Accordingly, each bit data can be closed within each bit. Therefore, a signal line crossing a bit becomes unnecessary, and the number of signal lines in the vertical direction can be suppressed to minimum, whereby a layout within the limited width is realized.
Note that there are disadvantages to this.
Firstly, because the individual bits of the counters 6-2 become distant from each other by a distance corresponding to each data storage region (memory) 6-5 for horizontal transfer (column-direction transfer), a large wiring capacitance and a large wiring resistance are added. This increases the operating current and causes degradation of the operation speed.
A second problem is that signal lines LBS that connect the individual bits of the counters cross the horizontal transfer signal lines LHTC, and driving noise of the counters 6-2 is placed on the data transfer signal lines 9-1, 9-2, 9-3, . . .
Also, whereas the counters 6-2 in each column operate at the same time, because the data transfer signal lines 9 are signal lines shared in the horizontal direction (column direction), all the counter noise in the individual columns is received by the data transfer signal lines 9, which results in serious noise for data transfer.